/*
 * P1022 DS 36Bit Physical Address Map Device Tree Source
 *
 * Copyright 2010 Freescale Semiconductor, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/dts-v1/;
/ {
	model = "fsl,P1022";
	compatible = "fsl,P1022DS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,P1022@0 {
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};

		PowerPC,P1022@1 {
			device_type = "cpu";
			reg = <0x1>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
	};

	localbus@fffe05000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
		reg = <0 0xffe05000 0 0x1000>;
		interrupts = <19 2 0 0>;

		ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
			  0x1 0x0 0xf 0xe0000000 0x08000000
			  0x2 0x0 0x0 0xffa00000 0x00040000
			  0x3 0x0 0xf 0xffdf0000 0x00008000>;

		nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;

			partition@0 {
				reg = <0x0 0x03000000>;
				label = "ramdisk-nor";
				read-only;
			};

			partition@3000000 {
				reg = <0x03000000 0x00e00000>;
				label = "diagnostic-nor";
				read-only;
			};

			partition@3e00000 {
				reg = <0x03e00000 0x00200000>;
				label = "dink-nor";
				read-only;
			};

			partition@4000000 {
				reg = <0x04000000 0x00400000>;
				label = "kernel-nor";
				read-only;
			};

			partition@4400000 {
				reg = <0x04400000 0x03b00000>;
				label = "jffs2-nor";
			};

			partition@7f00000 {
				reg = <0x07f00000 0x00080000>;
				label = "dtb-nor";
				read-only;
			};

			partition@7f80000 {
				reg = <0x07f80000 0x00080000>;
				label = "u-boot-nor";
				read-only;
			};
		};

		nand@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,elbc-fcm-nand";
			reg = <0x2 0x0 0x40000>;

			partition@0 {
				reg = <0x0 0x02000000>;
				label = "u-boot-nand";
				read-only;
			};

			partition@2000000 {
				reg = <0x02000000 0x10000000>;
				label = "jffs2-nand";
			};

			partition@12000000 {
				reg = <0x12000000 0x10000000>;
				label = "ramdisk-nand";
				read-only;
			};

			partition@22000000 {
				reg = <0x22000000 0x04000000>;
				label = "kernel-nand";
			};

			partition@26000000 {
				reg = <0x26000000 0x01000000>;
				label = "dtb-nand";
				read-only;
			};

			partition@27000000 {
				reg = <0x27000000 0x19000000>;
				label = "reserved-nand";
			};
		};

		board-control@3,0 {
			compatible = "fsl,p1022ds-pixis";
			reg = <3 0 0x30>;
			interrupt-parent = <&mpic>;
			/*
			 * IRQ8 is generated if the "EVENT" switch is pressed
			 * and PX_CTL[EVESEL] is set to 00.
			 */
			interrupts = <8 8 0 0>;
		};
	};

	soc@fffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "fsl,p1022-immr", "simple-bus";
		ranges = <0x0 0xf 0xffe00000 0x100000>;
		bus-frequency = <0>;		// Filled out by uboot.

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <12>;
		};

		ecm@1000 {
			compatible = "fsl,p1022-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <16 2 0 0>;
		};

		memory-controller@2000 {
			compatible = "fsl,p1022-memory-controller";
			reg = <0x2000 0x1000>;
			interrupts = <16 2 0 0>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2 0 0>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2 0 0>;
			dfsrr;

			wm8776:codec@1a {
				compatible = "wlf,wm8776";
				reg = <0x1a>;
				/*
				 * clock-frequency will be set by U-Boot if
				 * the clock is enabled.
				 */
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2 0 0>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2 0 0>;
		};

		spi@7000 {
			cell-index = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,espi";
			reg = <0x7000 0x1000>;
			interrupts = <59 0x2 0 0>;
			espi,num-ss-bits = <4>;
			mode = "cpu";

			fsl_m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,espi-flash";
				reg = <0>;
				linux,modalias = "fsl_m25p80";
				spi-max-frequency = <40000000>; /* input clock */
				partition@0 {
					label = "u-boot-spi";
					reg = <0x00000000 0x00100000>;
					read-only;
				};
				partition@100000 {
					label = "kernel-spi";
					reg = <0x00100000 0x00500000>;
					read-only;
				};
				partition@600000 {
					label = "dtb-spi";
					reg = <0x00600000 0x00100000>;
					read-only;
				};
				partition@700000 {
					label = "file system-spi";
					reg = <0x00700000 0x00900000>;
				};
			};
		};

		ssi@15000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x15000 0x100>;
			interrupts = <75 2 0 0>;
			fsl,mode = "i2s-slave";
			codec-handle = <&wm8776>;
			fsl,playback-dma = <&dma00>;
			fsl,capture-dma = <&dma01>;
			fsl,fifo-depth = <15>;
			fsl,ssi-asynchronous;
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,eloplus-dma";
			reg = <0xc300 0x4>;
			ranges = <0x0 0xc100 0x200>;
			cell-index = <1>;
			dma00: dma-channel@0 {
				compatible = "fsl,ssi-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupts = <76 2 0 0>;
			};
			dma01: dma-channel@80 {
				compatible = "fsl,ssi-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupts = <77 2 0 0>;
			};
			dma-channel@100 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupts = <78 2 0 0>;
			};
			dma-channel@180 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupts = <79 2 0 0>;
			};
		};

		gpio: gpio-controller@f000 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8572-gpio";
			reg = <0xf000 0x100>;
			interrupts = <47 0x2 0 0>;
			gpio-controller;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,p1022-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>; // L2, 256K
			interrupts = <16 2 0 0>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupts = <20 2 0 0>;
			};
			dma-channel@80 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupts = <21 2 0 0>;
			};
			dma-channel@100 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupts = <22 2 0 0>;
			};
			dma-channel@180 {
				compatible = "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupts = <23 2 0 0>;
			};
		};

		usb@22000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-usb2-dr";
			reg = <0x22000 0x1000>;
			interrupts = <28 0x2 0 0>;
			phy_type = "ulpi";
		};

		mdio@24000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-mdio";
			reg = <0x24000 0x1000 0xb0030 0x4>;

			phy0: ethernet-phy@0 {
				interrupts = <3 1 0 0>;
				reg = <0x1>;
			};
			phy1: ethernet-phy@1 {
				interrupts = <9 1 0 0>;
				reg = <0x2>;
			};
		};

		mdio@25000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,etsec2-mdio";
			reg = <0x25000 0x1000 0xb1030 0x4>;
		};

		enet0: ethernet@B0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			fsl,magic-packet;
			fsl,wake-on-filer;
			local-mac-address = [ 00 00 00 00 00 00 ];
			fixed-link = <1 1 1000 0 0>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
			queue-group@0{
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xB0000 0x1000>;
				interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
			};
			queue-group@1{
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xB4000 0x1000>;
				interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
			};
		};

		enet1: ethernet@B1000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "fsl,etsec2";
			fsl,num_rx_queues = <0x8>;
			fsl,num_tx_queues = <0x8>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			fixed-link = <1 1 1000 0 0>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
			queue-group@0{
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xB1000 0x1000>;
				interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
			};
			queue-group@1{
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xB5000 0x1000>;
				interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
			};
		};

		sdhci@2e000 {
			compatible = "fsl,p1022-esdhc", "fsl,esdhc";
			reg = <0x2e000 0x1000>;
			interrupts = <72 0x2 0 0>;
			fsl,sdhci-auto-cmd12;
			/* Filled in by U-Boot */
			clock-frequency = <0>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
				     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
				     "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2 0 0 58 2 0 0>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x97c>;
			fsl,descriptor-types-mask = <0x3a30abf>;
		};

		sata@18000 {
			compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
			reg = <0x18000 0x1000>;
			cell-index = <1>;
			interrupts = <74 0x2 0 0>;
		};

		sata@19000 {
			compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
			reg = <0x19000 0x1000>;
			cell-index = <2>;
			interrupts = <41 0x2 0 0>;
		};

		power@e0070{
			compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
			reg = <0xe0070 0x20>;
		};

		display@10000 {
			compatible = "fsl,diu", "fsl,p1022-diu";
			reg = <0x10000 1000>;
			interrupts = <64 2 0 0>;
		};

		timer@41100 {
			compatible = "fsl,mpic-global-timer";
			reg = <0x41100 0x100 0x41300 4>;
			interrupts = <0 0 3 0
			              1 0 3 0
			              2 0 3 0
			              3 0 3 0>;
		};

		timer@42100 {
			compatible = "fsl,mpic-global-timer";
			reg = <0x42100 0x100 0x42300 4>;
			interrupts = <4 0 3 0
			              5 0 3 0
			              6 0 3 0
			              7 0 3 0>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <4>;
			reg = <0x40000 0x40000>;
			compatible = "fsl,mpic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,p1022-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0 0 0
				0xe1 0 0 0
				0xe2 0 0 0
				0xe3 0 0 0
				0xe4 0 0 0
				0xe5 0 0 0
				0xe6 0 0 0
				0xe7 0 0 0>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,p1022-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@fffe09000 {
		compatible = "fsl,p1022-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xf 0xffe09000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 4 1
			0000 0 0 2 &mpic 5 1
			0000 0 0 3 &mpic 6 1
			0000 0 0 4 &mpic 7 1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@fffe0a000 {
		compatible = "fsl,p1022-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xf 0xffe0a000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 0 1
			0000 0 0 2 &mpic 1 1
			0000 0 0 3 &mpic 2 1
			0000 0 0 4 &mpic 3 1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};


	pci2: pcie@fffe0b000 {
		compatible = "fsl,p1022-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xf 0xffe0b000 0 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 8 1
			0000 0 0 2 &mpic 9 1
			0000 0 0 3 &mpic 10 1
			0000 0 0 4 &mpic 11 1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
